Benq AWL700 Wireless Router User Manual ISL3873

Benq Corporation Wireless Router ISL3873

Contents

users manual 2

1TMFile Number 4868.2CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.1-888-INTERSIL or 321-724-7143 |Intersil and Design is a trademark of Intersil Americas Inc.Copyright © Intersil Americas Inc. 2001, All Rights ReservedISL3873Wireless LAN Integrated Medium AccessController with Baseband ProcessorThe Intersil ISL3873 Wireless LANIntegrated Medium Access Controllerwith Integrated Baseband Processoris part of the PRISM® 2.4GHz radiochip set. The ISL3873 directly interfaces with the Intersil’s IFQMODEM (HFA3783). Adding Intersil’s RF/IF Converter(ISL3685) and Intersil’s Power Amp (HFA3983) offers thedesigner a complete end-to-end WLAN Chip Set solution.Protocol and PHY support are implemented in firmwarethus, supporting customization of the WLAN solution.Firmware implements the full IEEE 802.11 Wireless LANMAC protocol. It supports BSS and IBSS operation underDCF, and operation under the optional Point CoordinationFunction (PCF). Low level protocol functions such asRTS/CTS generation and acknowledgment, fragmentationand de-fragmentation, and automatic beacon monitoring arehandled without host intervention. Active scanning isperformed autonomously once initiated by host command.Host interface command and status handshakes allowconcurrent operations from multi-threaded I/O drivers.Additional firmware functions specific to access pointapplications are also available.The ISL3873 has on-board A/Ds and D/A for analog I and Qinputs and outputs, for which the HFA3783 IF QMODEM isrecommended. Differential phase shift keying modulationschemes DBPSK and DQPSK, with data scramblingcapability, are available along with Complementary CodeKeying to provide a variety of data rates. Both Receive andTransmit AGC functions with 7-bit AGC control obtainmaximum performance in the analog portions of thetransceiver.Built-in flexibility allows the ISL3873 to be configuredthrough a general purpose control bus, for a range ofapplications. The ISL3873 is housed in a thin plastic BGApackage suitable for PCMCIA board applications.The ISL3873 is designed to provide maximum performancewith minimum power consumption. External pin layout isorganized to provide optimal PC board layout to all userinterfaces including PCMCIA and USB.New Features of the ISL3873• USB Host Interface Supports USB V1.1 at 12Mbps.• New Start Up Modes Allow the PCMCIA Card InformationStructure to be Initialized From a Serial EEPROM. ThisAllows Firmware to be Downloaded from the Host,Eliminating the Parallel Flash Memory Device• Firmware Can be Loaded from Serial Flash Memory• Zero Glue Connection to 16-Bit Wide SRAM Devices• Low Frequency Crystal Oscillator to Maintain Time andAllow Baseband Clock Source to Power off During SleepMode• Improved Performance of Internal WEP Engine• Improvements to Debug Mode Support Tracing ExecutionFrom on Chip Memory• Programmable MBUS Cycle Extension Allows Accessingof Slow Memory Devices Without Slowing the Clock• Complete DSSS Baseband Processor• RAKE Receiver with Decision Feedback Equalizer• Processing Gain. . . . . . . . . . . . . . . . . . . . FCC Compliant• Programmable Data Rate. . . . . . . . 1, 2, 5.5, and 11Mbps• Ultra Small Package . . . . . . . . . . . . . . . . . . . . . 14 x 14mm• Single Supply Operation. . . . . . . . . . . . . . . . . 2.7V to 3.6V• Modulation Methods. . . . . . . . DBPSK, DQPSK, and CCK• Supports Full or Half Duplex Operations• On-Chip A/D and D/A Converters for I/Q Data (6-Bit,22MSPS), AGC, and Adaptive Power Control (7-Bit)• Targeted for Multipath Delay Spreads 125ns at 11Mbps,250ns at 5.5Mbps• Supports Short Preamble and Antenna DiversityApplications• PC Card Wireless LAN Adapters• USB PCMCIA Wireless LAN Adapters• PCN / Wireless PBX / Wireless Local Loop• High Data Rate Wireless LAN Systems Targeting IEEE802.11b Standard• Wireless LAN Access Points and Bridge Products• Spread Spectrum WLAN RF Modems• TDMA or CSMA Packet Protocol Radios• PCI Wireless LAN Cards (Using Ext. Bridge Chip)• ISA, ISA PNP WLAN CardsOrdering InformationPARTNUMBER TEMP.RANGE (oC) PACKAGE PARTNUMBERISL3873IK -40 to 85 192 BGA V192.14x14ISL3873IK96 -40 to 85 Tape and Reel 1000 Units /ReelData Sheet February 2001Microsoft® and Windows® are registered trademarks of Microsoft Corporation.PRISM® is a registered trademark of Intersil Americas Inc.PRISM and design is a trademark of Intersil Americas Inc.
2Simplified Block DiagramPHYSERIALCONTROL(MMI)PRISM RADIORADIO AND SYNTHMICRO-MEMORYWEPPC CARDON-CHIPRAM44MHz CLOCK†DATAADDRESSSELECTEXTERNALHOSTDATAUSBON-CHIPROMSERIAL CONTROLINTERFACE(MDI)676666711ANT_SELRX_RF_AGCRX_IF_DETTHRESH.IFDACI ADCQ ADCBASEBAND PROCESSORTXADCI DACQ DACI/ODEMODAGCVREFRXQ±RXI±RX_IF_AGCTXQ±TXI±TX_IF_AGCTX_AGC_INDATA I/ODETECTCTLTXDACMEDIUM ACCESSISL3873USBTHE ISL3873 MUST BE SUPPLIED WITH ASEPARATE CLOCK WHEN USB IS USED.SOURCE †COMPUTERADDRESSCONTROLHOSTINTERFACE HOSTINTERFACEPROGRAMMEDMAC ENGINEENGINECONTROLLERTXALCMODCONTROLLERSRAM ANDFLASHMEMORYRF SECTIONISL3873
3ISL3873 Signal DescriptionsHOST INTERFACE PINSPIN NAME PIN I/O TYPE DESCRIPTIONHA0-9 5V tol, CMOS, Input, 50K Pull Down Host PC Card Address Input, Bits 0 to 9HCE1- 5V tol, CMOS, Input, 50K Pull Up Host PC Card Select, Low ByteHCE2- 5V tol, CMOS, Input, 50K Pull Up Host PC Card Select, High ByteHD0-15 5V tol, BiDir, 2mA, 50K Pull Down Host PC Card Data Bus, Bit 0 to 15HINPACK- CMOS Output, 2mA Host PC Card I/O Decode ConfirmationHIORD- 5V tol, CMOS, Input, 50K Pull Up Host PC Card I/O Space Read StrobeHIOWR- 5V tol, CMOS, Input, 50K Pull Up Host PC Card I/O Space Write StrobeHRDY/HIREQ- CMOS Output, 4mA Host PC Card interrupt Request (I/O Mode), also used as PC CardReady (Memory Mode) output which is asserted to indicate cardinitialization is completeHOE- 5V tol, CMOS, Input, 50K Pull Up Host PC Card Memory Attribute Space Output EnableHREG- 5V tol, CMOS, Input, 50K Pull Up Host PC Card Attribute Space SelectRESET 5V tol, CMOS, ST Input, 50K Pull Up Hardware Reset. Self-asserted by internal pull-up at power-on. Clocksignal CLKIN or XTALIN must be available before negation of Reset.Value of MD[15..0] copied to MDIR[15..0] and various control registerbits on the first MCLK following release of ResetHSTSCHG- CMOS Output, 4mA Host PC Card Status ChangeHWAIT- CMOS Output, 4mA Host Wait, asserted to indicate data transfer not complete and to forceforce host bus wait statesHWE- 5V tol, CMOS Input, 50K Pull Up Host PC Card Memory Attribute Space Write EnableUSB INTERFACE PINSPIN NAME PIN I/O TYPE DESCRIPTIONUSB+ CMOS BiDir, 2mA, (Also USB Transceiver) USB, MBUS Address Bit 20, or I/O as PL5USB- CMOS BiDir, 2mA, (Also USB Transceiver) USB, MBUS Address Bit 21, or I/O as PL6USB_DETECT Input, 5V tolerant, pull-down Sense USB VBUS to indicate cable attachmentMEMORY INTERFACE PINSPIN NAME PIN I/O TYPE DESCRIPTIONMUBE- / MA0 /MWEH-CMOS TS Output, 2mA MBUS Upper Byte Enable for x16 Memory; MBUS Address Bit 0 (byte)for x8 Memory; High Byte Write Enable for 2 x8 MemoriesMA1-18 CMOS TS Output, 2mA MBUS Address Bits 1 to 18PL4-MA19 CMOS BiDir, 2mA MBUS Address Bit 19MLBE- CMOS TS Output, 2mA, 50K Pull Up MBUS Lower Byte Enable, or I/O as PM2MOE- CMOS TS Output, 2mA Memory Output EnableMWE- / MWEL- CMOS TS Output, 2mA Low (or only) Byte Memory Write EnableRAMCS- CMOS TS Output, 2mA RAM SelectNVCS- CMOS TS Output, 2mA NV Memory SelectMD0-7 5V tol, CMOS, BiDir, 2mA, 100K Pull Up MBUS Low Data Byte, Bits 0 to 7MD8-15 5V tol, CMOS, BiDir, 2mA50K Pull-Downs on MD15, MD14, MD13, MD11,MD10, MD0950K Pull-Ups MD12, MD08MBUS High Data Byte, Bits 8 to 15Default power up states are defined by pull-up and pull-down internalresistors as shown. Device defaults to external EEPROM for boot upmode. Using external 10K resistors, configure these pins according toTable 4 to change power-up configurationISL3873
4MAC RADIO INTERFACE AND GENERAL PURPOSE PORT PINSPIN NAME PIN I/O TYPE DESCRIPTION OF FUNCTION(IF OTHER THAN I/O PORT)PJ4 CMOS BiDir, 2mA PE1PJ5 CMOS BiDir, 2mA, 50K Pull Up LE_IFPJ6 CMOS BiDir, 2mA LED1PJ7 CMOS BiDir, 2mA, 50K Pull Up RADIO_PEPK0 CMOS BiDir, 2mA, ST, 50K Pull Down LE_RFPK1 CMOS BiDir, 2mA, 50K Pull Down SYNTHCLKPK2 CMOS BiDir, 2mA, 50K Pull Down SYNTHDATAPK3 CMOS BiDir, 2mA PA_PEPK4 CMOS BiDir, 2mA PE2PK7 CMOS BiDir, 2mA CAL_ENPL3 CMOS BiDir, 2mA TR_SW_BARPL7 CMOS BiDir, 2mA, Pull Down TR_SWSERIAL EEPROM PORT PINSPIN NAME PIN I/O TYPE DESCRIPTIONPJ0 CMOS BiDir SCLK, Serial ClockPJ1 CMOS BiDir, 50K Pull Down SD, Serial Data OutPJ2 CMOS BiDir, 50K Pull Down MISO, Serial Data INTCLKIN (CS_) CMOS BiDir CS_, Chip SelectCLOCKS PORT PINSPIN NAME PIN I/O TYPE DESCRIPTIONCLKIN CMOS Input, 50K Pull Down External Clock Input to MCLK prescaler (at >= 2X Desired MCLKFrequency, Typically 44-48MHz)XTALIN Analog Input 32.768kHz Crystal InputXTALOUT CMOS Output, 2mA 32.768kHz Crystal OutputCLKOUT CMOS, TS Output, 2mA Internal Clock Output (Selectable as MCLK, TCLK, or TOUT0)BBP_CLK Input Baseband Processor Clock. The nominal frequency for this clock is44MHz. This is used internally to generate divide by 2 and 4 for thetransceiver clockBASEBAND PROCESSOR RECEIVER PORT PINSPIN NAME PIN I/O TYPE DESCRIPTIONRX_IF_AGC O Analog drive to the IF AGC controlRX_RF_AGC O Drive to the RF AGC stage attenuator. CMOS digitalRX_IF_DET I Analog input to the receive power A/D converter for AGC controlRXI, ±I Analog input to the internal 6-bit A/D of the In-phase received data. Balanced differential 10+/11-RXQ, ±I Analog input to the internal 6-bit A/D of the Quadrature received data. Balanced differential 13+/14-BASEBAND PROCESSOR TRANSMITTER PORT PINSPIN NAME PIN I/O TYPE DESCRIPTIONTX_AGC_IN I Input to the transmit power A/D converter for transmit AGC controlTX_IF_AGC O Analog drive to the transmit IF power controlTXI ±O TX Spread baseband I digital output data. Data is output at the chip rate. Balanced differential 23+/24-TXQ ±O TX Spread baseband Q digital output data. Data is output at the chip rate. Balanced differential29+/30-ISL3873
5MISC CONTROL PORT PINSPIN NAME PIN I/O TYPE DESCRIPTIONANTSEL O The antenna select signal changes state as the receiver switches from antenna toantenna during the acquisition process in the antenna diversity mode. This is acomplement for ANTSEL (pin 40) for differential drive of antenna switchesANTSEL O The antenna select signal changes state as the receiver switches from antenna toantenna during the acquisition process in the antenna diversity mode. This is acomplement for ANTSEL (pin 39) for differential drive of antenna switchesTestMode I/O Factory level test pin. This pin must be pulled low with a 10K resistor.CompCap1 I Compensation CapacitorCompCap2 I Compensation CapacitorCompRes1 I Compensation ResistorCompRes2 I Compensation ResistorDBG(0-4) I/O Debug factory test signals. Do not connectPOWER PORT PINSPIN NAME PIN I/O TYPE DESCRIPTIONVDDA Power DC Power Supply 2.7 - 3.6V (Not Hardwired Together on Chip)VDD Power DC Power Supply 2.7 - 3.6VSUPPLY5V Power 5V Tolerant DC Power SupplyVSSA Ground Analog GroundVsub Ground Analog GroundGND Ground Digital GroundVREF Input Voltage Reference for A/D’s and D/A’sIREF Input Current Reference for internal ADC and DAC devices. Requires 12K resistor to ground.ST = Schmitt Trigger (Hysteresis), TS = Three-State. Signals ending with “-” are active low.ISL3873 PIN NUMBER ASSIGNMENTSPIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAMEA1 NC C7 HD4 F4 MA5 K16 VDDA2 MA10 C8 HD6 F13 HD9A3 MA13 C9 HD14 F14 HD10 L1 MD8A4 MA16 C10 HD11 F15 HA2 L2 MD7A5 GND C11 HD7 F16 HA1 L3 MD10A6 PL4_MA19 C12 HA7 L4 MD9A7 DBG2 C13 GND G1 MD12 L13 GNDA8 VDD C14 DBG3 G2 MD14 L14 RX_RF_AGCA9 HD3 C15 NC G3 VDD L15 ANT_SELA10 HCE2 C16 RESET G4 MA2 L16 ANT_SELA11 GND G13 GNDA12 HD15 D1 MA3 G14 HSTSCHG M1 MD5A13 HA9 D2 MA8 G15 HD0 M2 VDDA14 VDD D3 MA7 G16 BBP_CLK M3 GNDA15 HA6 D4 MA14 M4 MD6A16 NC D5 MA17 H1 VDD M13 VDDAD6 DBG0 H2 MLBE M14 COMPCAP1B1 VDD D7 GND H3 MD11 M15 GNDISL3873
6B2 NC D8 HD5 H4 MD13 M16 VDDB3 MA9 D9 HIREQ H13 HD2B4 MA12 D10 HIOWR H14 HD1 N1 MD4B5 VDD D11 HOE H15 HA0 N2 MD0B6 MA18 D12 NC H16 HD8 N3 MD3B7 DBG1 D13 HA5 N4 MD2B8 HD12 D14 HWAIT J1 XTALIN N5 NCB9 HCE1 D15 SUPPLY5V J2 XTALOUT N6 PJ7(RADIO_PE)B10 VDD D16 HREG J3 RAMCS N7 PK2(SYNTHDATA)B11 HIORD J4 NVCS N8 VDDAB12 HA8 E1 GND J13 USB_DET N9 VSSAB13 HWE E2 MA4 J14 VDD N10 VSUBB14 HA4 E3 GND J15 USB- N11 VDDB15 NC E4 NC J16 USB+ N12 IREFB16 DBG4 E13 HA3 N13 VSSAE14 VDD K1 CLKIN N14 NCC1 MA6 E15 HINPACK K2 MOE N15 RX_IF_AGCC2 NC E16 GND K3 MWEL N16 TX_IF_AGCC3 MA11 K4 GNDC4 MA15 F1 MD15 K13 TESTMODEC5 CLKOUT F2 MA1 K14 GNDC6 HD13 F3 MWEH_MA0 K15 GNDP1 MD1 R1 PJ1(SDATA)T1 PJ0(SCLK)P2 PJ2(MISO)R2 NC T2 VDDP3 TCLKIN R3 NC T3 PJ6(LED1)P4 PJ5(LE_IF)R4 PJ4(PE1)T4 PK1(SYNTHCLK)P5 GND R5 PK0(LE_RF)T5 PK4(PE2)P6 PL7(TR_SW)R6 PK3(PA_PE)T6 PL3(TR_SW_BAR)P7 PK7(CAL_EN)R7 RXI+ T7 RXI-P8 VDDA R8 VDDA T8 VDDAP9 GND R9 RXQ+ T9 RXQ-P10 VSUB R10 RX_IF_DET T10 TX_AGC_INP11 VREF R11 VDDA T11 VSSAP12 VDDA R12 TXI+ T12 TXI-P13 COMPRES2 R13 COMCAP2 T13 VSSAP14 N C R14 TXQ+ T14 TXQ-P15 NC R15 NC T15 COMPRES1P16 NC R16 NC T16 NCISL3873 PIN NUMBER ASSIGNMENTS (CONTINUED)PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAMEISL3873
7Absolute Maximum Ratings Thermal InformationSupply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6VInput, Output or I/O Voltage . . . . . . . . . . . .GND -0.5V to VCC +0.5VESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2Operating ConditionsVoltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3VAmbient Temperature Range. . . . . . . . . . . . . . . . . . . -40oC to 85oCThermal Resistance (Typical, Note 1) θJA (oC/W)BGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oCMaximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .100oCMaximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC(Lead Tips Only)CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of thedevice at these or any other conditions above those indicated in the operational sections of this specification is not implied.NOTE:1. θJA is measured with the component mounted on an evaluation PC board in free air.DC Electrical SpecificationsPARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITSPower Supply Current ICCOP VCC = 3.6V, CLK Frequency 44MHz - - 175 mAInput Leakage Current IIVCC = Max, Input = 0V or VCC -10 1 10 mAOutput Leakage Current IOVCC = Max, Input = 0V or VCC -10 1 10 mALogical One Input Voltage VIH VCC = Max, Min 0.7VCC --VLogical Zero Input Voltage VIL VCC = Min, Max - - 0.3V VLogical One Output Voltage VOH IOH = -1mA, VCC = Min 0.9VCC --VLogical Zero Output Voltage VOL IOL = 2mA, VCC = Min - 0.1 0.1VCC VInput Capacitance CIN CLK Frequency 1MHz. All measurementsreferenced to GND. TA = 25oC- 5 10 pFOutput Capacitance COUT CLK Frequency 1MHz. All measurementsreferenced to GND. TA = 25oC- 5 10 pFNOTE: All values in this table have not been measured and are only estimates of the performance at this time.AC Electrical SpecificationsPARAMETER SYMBOL MIN TYP MAX UNITSCLOCK SIGNAL TIMINGOSC Clock Period (Typ. 44MHz) tCYC 20 20.8 200 nsHigh Period tH1 10 10.4 - -Low Period tL1 10 10.4 - -EXTERNAL MEMORY READ INTERFACEMOE-Setup Time from RAMCS_ tS1 0--nsMOE_Setup Time from MA (17..0) tS2 0--nsMA (17..1) Hold Time from MOE_ Rising Edge tH1 20 - - nsRAMCS_ Hold from MOE_ Rising Edge tH2 20 - - nsMD (15..0) Enable from MOE_ Falling tE1 5--nsMO (15..0) Disable from MOE_ Rising Edge tD1 --100 nsEXTERNAL MEMORY WRITE INTERFACEMA (17..0) Setup to MWE_ Falling Edge tS3 000nsRAMCS_ Setup to MWE tS4 0--nsMA (17..0) Hold from MWE_ Rising Edge tH3 15 - - nsRAMCS _ Hold from MWE_ Rising Edge tH4 15 - - nsMD (15..0) Setup to MWE_ Rising Edge tS5 40 - - nsMD (15..0) Hold from MWE_ Rising Edge tH5 15 - - nsSYNTHESIZERSYNTHCLK(PK1) Period tCYC 83 - 4,000 nsISL3873
8SYNTHCLK(PK1) Width Hi tH1 tCYC/2 - 10 - tCYC/2 + 10 nsSYNTHCLK(PK1) Width Lo tL1 tCYC/2 - 10 - tCYC/2 + 10 nsSERIAL PORTSYNTHCLK(PK1) Clock Period tCYC 83ns - 4000 nsLow Width tH1, tL1 tCYC/2 -10 - tCYC/2 + 10 nsDelay from Clock Falling Edge to SPCSx, SPAS, SPREAD,SYNTHDATA(PK2) OutputstCD -10-nsSetup Time of SYTHNDATA(PK2) Read to SYTHNCLK(PK1) Falling Edge tDRS 15 - - nsHold Time of SYTHNDATA(PK2) Read from SYTHNCLK(PK1) Falling Edge tDRH 0--Hold Time of SYTHNDATA(PK2) Write from SYTHNCLK(PK1) Falling Edge tDWH 0--SYSTEM INTERFACE - PC CARD IO READ 16Data Delay After HIORD- tDIORD - - 100 nsData Hold Following HIORD- tHIORD 0--nsHIORD- Width Time tWIORD 165 - - nsAddress Setup Before HIORD- tSUA 70 - - nsAddress Hold Following HIORD- tHA 20 - - nsHCE(1,2)- Setup Before HIORD- tSUCE 5--nsHCE(1,2)- Hold After HIORD- tHCE 20 - - nsHREG- Setup Before HIORD- tSUREG 5--nsHREG- Hold Following HIORD- tHREG 0--nsHINPACK- Delay Falling from HIORD- tDFINPACK 0 - 45 nsHINPACK- Delay Rising from HIORDN dDRINPACK 30 - 45 nsHWAIT- tDFWT - - 35 nsData Delay from HWAIT- Rising tDRWT --0nsHWAIT- Width Time tWWT - - 12,000 nsSYSTEM INTERFACE - PC CARD IO WRITE 16Data Setup Before HIOWR- tSUIOWR 30 - 92 nsData Hold Following HIOWR- tHIOWR 20 - - nsHIOWRN- Width Time tWIOWR 165 - - nsAddress Setup Before HIOWR- tSUA 70 - - nsAddress Hold Following HIOWR- tHA 20 - - nsHCE(1,2)- Setup Before HIOWR- tSUCE 5--nsHCE(1,2)- Hold Following HIOWR- tHCE 20 - - nsHREG- Setup Before HIOWR- tSUREG 5--nsHREG- Hold Following HIOWR- tHREG 0--nsHWAIT- Delay Falling from HIOWR- tDFWT - - 35 nsHWAIT- Width Time tWWT - - 12,000 nsHIOWRN High from HWAIT- High tDRIOWR 0--nsBASEBAND SIGNALSFull Scale Input Voltage (VP-P) 0.25 0.50 1.0 VInput Bandwidth (-0.5dB) - 20 - MHzInput Capacitance -5-pFInput Impedance (DC) 5--kΩFS (Sampling Frequency) - - 22 MHzAC Electrical Specifications (Continued)PARAMETER SYMBOL MIN TYP MAX UNITSISL3873
9WaveformsFIGURE 1. EXTERNAL MEMORY READ TIMINGFIGURE 2. EXTERNAL MEMORY WRITE TIMINGFIGURE 3. SYNTHESIZERADDRESSMA(17..1)tH1tE1tS2tH2RAMCS_MOE_MD(15..0)tS1tD1ADDRESSMA(17..1)tH5tH4tS4tS3tH3RAMCS_MWE_MD(15..0)tS5SYNTHCLKSYNLESPCSPWRSYNTHDATAtH1 tL1tCYCtD1 tD2tD3D[n] D[n -1] D[n -2] D[2] D[1] D[0]ISL3873
10FIGURE 4. PC CARD IO READ 16FIGURE 5. PC CARD IO WRITE 16Waveforms (Continued)HA[15:0]HREG-HCE(1, 2) -HIORD-HINPACK-HWAIT-HD[15:0]tSUREGISUCEtHREGtHCEtWIORDtDIORDtDFINPACKtSUAtDFWT tDRWTtHIORDtDRINPACKtHAtWWTHA[15:0]HREGN-HCE (1, 2) -HIOWR-HWAIT-HD[15:0]tSUREG tHREGtHAtHCEtSUCEtSUAtDFWTtSUIOWR tWWT tHIOWRtDRIOWRtWIOWRtDRINPACKISL3873
11IISL3873 MAC System OverviewFIGURE 6. 8-BIT MEMORY INTERFACE REQUIREMENTS FOR ISL3873FIGURE 7. 16-BIT MEMORY INTERFACE REQUIREMENTS FOR ISL3873ISL3873MD0..15MA1..17NVCS_MOE_MWEL_MA0/MWEH_RAMCS_FLASH128Kx8MD0..7MA0..16CS_OE_SRAM128Kx8MD8..15MA1..17WE_CS_SRAM128Kx8MD0..7MA1..17OE_CS_WE_OE_ISL3873MD0..15MA1..17NVCS-MOE-MWEL-MA0/MWEH-RAMCS-FLASHDATA(0..15)ADDR(0..16)CE-OE-SRAMDATA(0..15)ADDR(0..16)UB-LB-CE-OEWEMLBE-WE128Kx16128Kx16ISL3873
12External Memory InterfaceThe ISL3873 provides separate external chip selects forcode space and data storage space. Code space isaccessible as data space through an overlay mechanism,except for an internal ROM. Refer to Figures 6, 7 and 8 forISL3873 memory configuration detail examples.The maximum possible memory space size is 4Mbytes. IfUSB is the host interface, this is reduced to 1Mbyte.Most of the data store space is reserved for storage ofreceived and transmitted data, with some areas reserved foruse by firmware. However, a portion of the data store may beallocated as code store. This permits higher speedinstruction execution, by using fast RAMs, than is possiblefrom Flash memories. The maximum size of this overlay isthe full code space address range, 128Kbytes, and isallocated in independent sections of 16KBytes each, on16Kbyte boundaries, ranging from the highest address of theactual physical memory space and extending down.Mapping code execution to RAM requires the RAM to havecode written into it. Typically, this is done by placing code in anon-volatile memory such as a Flash in the code space. Atinitialization, the code in the non-volatile memory transfers itselfto RAM, maps the appropriate blocks of the code space to theRAM, and then branches to begin execution from RAM. Thisallows low cost, slow Flash devices to hold an entire codeimage, which can be executed much faster from RAM. If codeis not placed in an external non-volatile memory as describedhere, it must be transferred to the RAM via the Host Interface.Slow memories are not dynamically sensed. Following reset,the instruction clock operates with a slower cycle while theFlash is copied to RAM. Once code has been copied fromFlash to RAM, execution transfers to RAM and the clock israised to the normal operating frequency.As mentioned above, it is feasible to operate without a codeimage in a non-volatile memory. In such a system, thefirmware must be downloaded to RAM through the hostinterface before operation can commence.The external SRAM memory must be organized in a 16-bitwidth to provide adequate performance to implement the802.11 protocol at 11Mb/s rates. Systems designed for lowerperformance applications may be able to use 8-bit widememory.The minimum external memory is 128Kbytes of SRAM,organized 8 or 16 bits wide. Typical applications, including802.11 station designs, use 256Kbytes organized 128K x 16.An access point application could make use of the full addressspace of the device with 4Mbytes organized a 2M x 16.The ISL3873 supports 8 or 16-bit code space, and 8 or 16-bitdata space. Code space is typically populated with the leaseexpensive Flash memory available, usually an 8-bit device.Data space is usually populated with high-speed RAMsconfigured as a 16-bit space. This mixing of 8/16 bit spaces isfully supported, and may be done in any combination desiredfor code and data space.The ISL3873 supports direct control of single chip 16-bitwide SRAMs with high/low byte enables, as well as directcontrol of a 16-bit space constructed from 8-bit wide SRAMs.The type of memory configuration is specified via theappropriate MD pin, sensed when the ISL3873 is reset.ISL3873 pin MUBE-/MA0/MWEH- functions as Address 0 for8-bit access, (such as Flash) as MWEH (High Byte WriteEnable) when two x8 memories are configured as a singlex16 space, and as the upper Byte Enable when a single x16memory is used. No external logic is required to generatethe required signals for both types of memory configurations,even when both exist together; all that is required is for theISL3873 code to configure the ISL3873 memory controller togenerate the proper signals for the particular address spacebeing accessed.PULLUP45DB011PULLUPCS# (TCLKIN)SCLK (PJ0)SD (PJ1)MISO (PJ2)ISL3873LARGE SERIAL EEPROM SMALL SERIAL EEPROMISL3873PULLUPCS# (TCLKIN)SCLK (PJ0)NOTE: Must operate at 400kHz AT 3.3VDC24C08 (NOTE)A2A1AOSDASCLWPFIGURE 8. SERIAL EEPROM INTERFACESISCKSORESET#WP#CSISL3873
13For 8-bit spaces, the ISL3873 dynamically configures pinMUBE-/MA0/MWEH- cycle-by-cycle as the address LSB.MWEL-/MWE- is the only write control, and MOE- is the readoutput enable.For 16-bit spaces constructed from 8-bit memories, theISL3873 dynamically configures pin MUBE-/MA0/MWEH-cycle-by-cycle as the high byte write enable, MWEL- as the lowwrite enable signal, and MOE- as the read output enable.For 16-bit spaces constructed from single-chip x16memories (such as SRAMs), the ISL3873 dynamicallyconfigures pin MUBE_/MA0/MWEH- cycle-by-cycle as theupper byte enable. Pin MLBE- is connected as the low byteenable, MWEL-/MWE- is the write control, and MOE- is theread output enable.These memory implementations require no external logic.The memory spaces may each be constructed from any typeof memory desired. The only restriction is that a singlememory space must be constructed from the same type ofmemory; for example, data space may not use both x8 andx16 memories, it must be all x8, or all x16. This restrictiondoes not apply across memory spaces; e.g., code space mayuse a x8 memory and data space a single x16 memory, orcode space two x8 memories and data space a single x8memory.Serial EEPROM InterfaceThe ISL3873 contains a small on-chip ROM firmware whichwas added to allow the CIS or CIS plus firmware image to betransferred from an off-chip serial non-volatile memory deviceto RAM after a system reset. This allows a system configurationwithout a parallel Flash device. The operating frequency of theserial port is 400kHz with a voltage of 3.3V. Refer to Figure 8 foradditional details on configuring the serial memory to theISL3873. The Power On Reset Configuration section in thisdocument provides additional details on memory selection andcontrol after a Reset condition.PC Card InterfacePC Card Physical InterfaceThe Host interface is compatible to the PC Card 95 Standard(PCMCIA v2.1). The ISL3873 Host Interface pins connectdirectly to the correspondingly named pins on the PC Cardconnector with no external components (other than resistors)required. The ISL3873 operates as an I/O card using lessthan 64 octet locations. Reads and writes to internal registersand buffer memory are performed by I/O accesses. Attributememory (256 octets) is provided for the CIS table which islocated in external memory. Common memory is not used.The following describes specific features of various pins:HA[9:0]Decoding of the system address space is performed by theHCEx-. During I/O accesses HA[5:0] decode the register.HA[9:6] are ignored when the internal HAMASK register isset to the defaults used by the standard firmware. Duringattribute memory accesses HA[9:1] are used.HD[15:0]The host interface is primarily designed for word accesses,although all byte access modes are fully supported. SeeHCE1-, HCE2- for a further description. Note that attributememory is specified for and operates with even bytes accessesonly.HCE1-, HCE2-The PC Card cycle type and width are controlled with the CEsignals. Word and Byte wide accesses are supported, usingthe combinations of HCE1-, HCE2-, and HA0 as specified inthe PC Card standard.HWE-, HOE-HOE- and HWE- are only used to access attribute memory.Common Memory, as specified in the PC Card standard, isnot used in the ISL3873. HOE- is the strobe that enables anattribute memory read cycle. HWE- is the correspondingstrobe for the attribute memory write cycle. The attributespace contains the Card Information Structure (CIS) as wellas the Function Configuration Registers (FCR).HIORD-, HIOWR-HIORD- and HIOWR- are the enabling strobes for registeraccess cycles to the ISL3873. These cycles can only beperformed once the initialization procedure is complete andthe ISL3873 has been put into IO mode.HREG-This signal must be asserted for I/O or attribute cycles. Acycle where HREG- is not asserted will be ignored as theISL3873 does not support common memory.HINPACK-This signal is asserted by the ISL3873 whenever a valid I/Oread cycle takes place. A valid cycle is when HCE1-, HCE2-,HREG-, and HIORD- are asserted, once the initializationprocedure is complete.HWAIT-Wait states are inserted in accesses using HWAIT-. The hostinterface synchronizes all PC Card cycles to the internalISL3873 clock. The following wait states should be expected:Direct Read or Write to Hardware Register• 1/2 to 1 MCLK assertion of HWAIT- for internalsynchronization.Write to Memory Mapped Register, Buffer Access Path,or Attribute Space (Post-Write)• The data required for the write cycle will be latched andtherefore only the synchronizing wait state will occur.• Until the queued cycle has actually written to the memory,any subsequent access by the Host will result in a WAIT.ISL3873
14Read to Attribute Space and Memory Mapped Registers• WAIT will assert until the memory arbitration and accesshave completed.Buffer Access Paths, BAP0 and BAP1• An internal Pre-Read cycle to memory is initiated by ahost Buffer Read cycle, after the internal address pointerhas auto-incremented. If the next host cycle is a read tothe same buffer, the data will be available without amemory arbitration delay.• A single register holds the pre-read data. Thus, any readaccess to any other memory-mapped register (or the otherbuffer access path) will result in the pre-read databecoming invalidated.• If another read cycle has invalidated the pre-read, then amemory arbitration delay will occur on the next bufferaccess path read cycle.HIREQ-Immediately after reset, the HIREQ- signal serves as theRDY/BSY (per the PC Card standard). Once the ISL3873firmware initialization procedure is complete, HIREQ- isconfigured to operate as the interrupt to the PC Card socketcontroller. Both Level Mode and Pulse Mode interrupts aresupported. By default, Level mode interrupts are used, sothe interrupt source must be specifically acknowledged ordisabled before the interrupt will be removed.RESETWhen reset is de-asserted, the CIS table is initialized and,once complete, HIREQ- is set high (HIREQ- acts asRDY/BSY from reset and is set high to indicate the card isready for use). The CIS table resides in Flash memory and iscopied to RAM during firmware initialization. The hostsystem can then initialize the card by reading the CISinformation and writing to the configuration register.ISA PNPThe ISL3873 can be connected to the ISA bus and operatein a Plug and Play environment with an additional chip suchas the Fujitsu MB86703, Texas Instruments TL16PNP200A,or Fairchild Semiconductor NM95MS15. See the ApplicationNote AN9874, “ISA Plug and Play with the HFA3841” formore details.Register InterfaceThe logical view of the ISL3873 from the host is a block of 32word wide registers. These appear in IO space starting atthe base address determined by the socket controller. Thereare three types of registers.Hardware Registers (HW)• 1 to 1 correspondence between addresses and registers.• No memory arbitration delay, data transfer directly to/fromregisters.• AUX base and offset are write-only, to set up accessthrough AUX data port.Note: All register cycles, including hardware registers, incura short wait state on the PC Card bus to insure the hostcycle is synchronized with the ISL3873's internal MCLK.Memory Mapped Registers in Data RAM (MM)• 1 to 1 correspondence.• Requires memory arbitration, since registers are actuallylocations in ISL3873 memory.• Attribute memory access is mapped into RAM as Base-address + 0x400.• AUX port provides host access to any location in ISL3873RAM (reserved).Buffer Access Path (BAP)• No 1 to 1 correspondence between register address andmemory address (due to indirect access through bufferaddress pointer registers).• Auto increment of pointer registers after each access.• Require memory arbitration since buffers are located inISL3873 memory.• Buffer access may incur additional delay for HardwareBuffer Chaining.Buffer Access PathsThe ISL3873 has two independent buffer access paths, whichpermits concurrent read and write transfers. The firmwareprovides dynamic memory allocation between Transmit andReceive, allowing efficient memory utilization. On-the-flyallocation of (128-byte) memory blocks as needed for receptionwastes minimal space when receiving fragments. The ISL3873hides management of free memory from the driver, and allowsfast response and minimum data copying for low latency. Thefirmware provides direct access to TX and RX buffers based onFrame ID (FID). This facilitates Power Management queuing,and allows dynamic fragmentation and de-fragmentation by thecontroller. Simple Allocate/De-allocate commands ensure lowhost CPU overhead for memory management.Hardware buffer chaining provides high performance whilereading and writing buffers. Data is transferred between thehost driver and the ISL3873 by writing or reading a singleregister location (the Buffer Access Path, or BAP). Eachaccess increments the address in the buffer memory.Internally, the firmware allocates blocks of memory as neededto provide the requested buffer size. These blocks may not becontiguous, but the firmware builds a linked list of pointersbetween them. When the host driver is transferring datathrough a buffer access path and reaches the end of aphysical memory block, hardware in the host interface followsthe linked list so that the buffer access path points to thebeginning of the next memory block. This process iscompletely transparent to the host driver, which simply writesor reads all buffer data to the same register. If the host driverattempts to access beyond the end of the allocated buffer,subsequent writes are ignored, and reads will be undefined.ISL3873
15USB PortThe USB interface implemented in the ISL3873 complieswith the Universal Serial Bus Specification Revision 1.1.dated September 23, 1998, which is available from the USBImplementers’ Forum at http://www.usb.org/.The USB supports 4 endpoints.• One Communications Class control endpoint for interfacemanagement;• One Communications Class interrupt endpoint forsignalling interrupts to the host; and,• Two Bulk endpoints for transfer of encapsulated NDISfunctions to and from the host.The USB along with USB support firmware provides analternate host interface for attaching an 802.11{b} WLANadapter to a host computer. This interface does not provide“wireless USB” where USB packets are sent on the wirelessmedium due to timing constraints in the USB protocol.USB+ and USB- are the differential pair signals provided forthe user. These signals are capable of directly driving a USBcable.USB_DETECT is a 5V tolerant input to the ISL3873 device.It is used to signal the MAC processor that a USB cable isattached to the unit.Complete details on the USB firmware for controlling thisport can be obtained by contacting the factory directly.Power SequencingThe ISL3873 provides a number of firmware controlled portpins that are used for controlling the power sequencing andother functions in the front end components of the radio.Packet transmission requires precise control of the radio.Ideally, energy at the antenna ceases after the last symbol ofinformation has been transmitted. Additionally, thetransmit/receive switch must be controlled properly to protectthe receiver. It's also important to apply appropriatemodulation to the PA while it's active.Signaling sequences for the beginning and end of normaltransmissions are illustrated in Figure 10. Table 1 listsapplicable delays associated with these control signals.A transmission begins with PE2 as shown in Figure 10. Next,the transmit/receive switch is configured for transmission viathe differential pair TR_SW and TR_SW_BAR. This isfollowed by a transmit enable (TX_ENABLE) to theBaseband processor inside the ISL3873. This enableactivates the transmit state machine in the BBP. Lastly,PA_PE activates the PA. Delays for these signals related tothe initiation of transmission are referenced to PE2.Immediately after the final data bit has been clocked out of theMAC the Baseband processor is disabled. The MAC then waitsfor a control signal (TX_READY) from the Baseband processorto go inactive, signaling that the BBP has modulated the finalinformation-rich symbol. It then immediately de-asserts PA_PEfollowed by placing the transmit/receive switch in the receiveposition and ending with PE2 going high. Delays for thesesignals related to the termination of transmission arereferenced to the rising edge of PE2.PE1 and PE2 encoding details are found in Table 2.Note that during normal receive and transmit operation thatPE1 is static and PE2 toggles for receive and transmitstates.FIGURE 9. BLOCK DIAGRAM OF A BUFFER ACCESS PATHBUFFER DESCRIPTORACCESS (FIRMWARE)ALLOCATE/DEALLOCATEREQUEST BLOCKOFFSETVIRTUALFRAME BUFFERDATA PORTPRE-READ/POST-WRITEOFFSET CENTERHOSTBUSSTATUSHEADERDATABUFFERMEMORYAFIDDTABLE 1. TRANSMIT CONTROL TIMING SPECIFICATIONSPARAMETER SYMBOL DELAY TOLERANCE UNITSPE2 to TR Switch tD1 2±0.1 µsPE2 to PA_PE tD3 3±0.1 µsPA_PE to PE2 tD4 3±0.1 µsTR Switch to PE2 tD5 2±0.1 µsISL3873
16Master ClockPrescalerThe ISL3873 contains a clock prescaler to provide flexibility inthe choice of clock input frequencies. For 11Mb/s operation, theinternal master clock, MCLK, must be between 11MHz and16MHz. The clock generator itself requires an input from theprescaler that is twice the desired MCLK frequency. Thus thelowest oscillator frequency that can be used for an 11MHzMCLK is 22MHz. The prescaler can divide by integers and 1/2steps (IE 1, 1.5, 2, 2.5). Another way to look at it is that thedivisor ratio between the external clock source and the internalMCLK may be integers between 2 and 14.Typically, the 44MHz baseband clock is used as the input, andthe prescaler is set to divide by 2. Another useful configurationis to set the prescaler to divide by 1.5 (resulting in 44MHz ÷3)for an MCLK of 14.67MHz. Contact the factory for furtherdetails on setting the clock prescaler register in the ISL3873.Low-Frequency CrystalThe ISL3873 MAC controller can accept the same clock signalas the PHY baseband processor (typically 44MHz), therebyavoiding the need for a separate, MAC-specific oscillator. TheISL3873 input has a low-frequency oscillator. This low-frequency oscillator is intended for use with a 32.768KHz,tuning-fork type watch crystal to permit accurate timekeepingwith very low power consumption during sleep state.If a 32.768KHz crystal is connected, the resulting LF clock issupplied to an interval timer to permit measuring sleepintervals as well as providing a programmable wake-up time.In addition, the clock generator can operate either from CLKINor (very slowly) from the LF clock. Glitch-free switchingbetween these two clock sources, under firmware control, isprovided by two, non-architectural Strobe functions (“FAST”and “SLOW”). In addition, during hardware reset, the clockgenerator source is set to the LF clock if no edges aredetected on CLKIN for two cycles of the LF clock (roughly 61microseconds). This allows proper initialization with omissionof either clock source, since without the LF crystal attachedthere will not be cycles of the LF clock to activate the detectioncircuit. The ability to initialize the ISL3873 using the LFoscillator to generate MCLK allows the high-frequency (PHY)oscillator to be powered down during sleep state. If this isdone, firmware can turn on power to the PHY oscillator uponwake-up, and use the interval timer to measure the start-upand stabilization period before switching to use CLKIN.Clock GeneratorThe ISL3873 can operate with MCLK frequencies up to at least25MHz and CLKIN frequencies of at least 50MHz. The MCLKprescaler generates MCLK (and QCLK) from the external clockprovided at the CLKIN input, or from the output of the LFoscillator. The MCLK prescaler divides the selected input clockby any integer value between 2 and 16, inclusive.• When using a 44MHz CLKIN, as is typical for 802.11 or802.11b controllers with a PC Card Host Interface, commondivisors are 3 (14.67MHz), 4 (11MHz), or 5 (8.8MHz)• When using a 48MHz CLKIN, as is typical for 802.11 or802.11b controllers with a USB host interface, commondivisors are 3 (16MHz), 4 (12MHz), or 6 (8MHz)The MCLK prescaler is set to divide by 16 at hardware resetto allow initialization firmware to be executed from slowFIGURE 10. TRANSMIT CONTROL SIGNAL SEQUENCINGPE1PE2TR_SWTR_SW_BARPA_PEtD1 tD5tD3 tD4TABLE 2. POWER ENABLE STATESPE1 PE2 PLL_PEPower Down State 0 0 1Receive State 1 1 1Transmit State 1 0 1PLL Active State 0 1 1PLL Disable State X X 0PLL_PE is controlled via the serial interface, and can be used todisable the internal synthesizer, the actual synthesizer control isan AND function of PLL_PE, and a result of the OR function ofPE1 and PE2. PE1 and PE2 will directly control the power enablefunctionality of the LO buffer(s)/phase shifter.ISL3873
17memory devices at any CLKIN frequency. The MCLKprescaler generates glitch free output when the divisor ischanged. This allows firmware to change the MCLKfrequency during operation, which is especially useful toselectively reduce operating speed, thereby conservingpower, when full speed processing is not required.Power On Reset ConfigurationPower On Reset is issued to the ISL3873 with the RESETpin or via the soft reset bit, SRESET, in the ConfigurationOption Register (COR, bit 7). RESET originates from theHOST system which applies RESET for at least 0.01ms afterVCC has reached 90% of its end value (see PC-Cardstandard, Vol. 2, Ch. 4.12.1).The MD[15:8] pin values are sampled during RESET orSoftware Reset (SRESET). These pins have internal 50Kresistors. External pull-up or pull-down resistors (typically10kΩ) are used for bits which need to be configureddifferently than the default.Table 3 summarizes the effect per pin. Table 4 provides theMD15 and MD14 bit values required to allow the ISL3873 touse Serial EEPROM option.MD[11], StrIdle, has no equivalent functionality in any controlregister. When asserted at reset, it will inhibit firmwareexecution. This is used to allow the initial download offirmware in “Genesis Mode”. See the Hardware ReferenceManual for more details. The latch is cleared when theSoftware Reset, SRESET, COR(7) is active.XTALINXTALOUTX1C1C2FIGURE 11. 32.768kHz CRYSTAL10MΩ22pF4700pFTABLE 3. INITIALIZATION STRAPPING OPTIONS ON MBUS DATA PINSBITS NAME DEFAULT FUNCTION15:14 NVtype[1:0] 30 Indicates type of serial NV memory to be read by initialization firmware in on-chip ROM.Up to 8 NV device types can be encoded with (StrIdle or NVtype). If StrIdle = 0, NV memory holds a firmwareimage, and NVtype identifies 1 of 4 “large” (. = 128Kb) types. If StrIdle = 1, the NV memory just holds the CIS,and NVtype identifies 1 of 4 “small” (< = 8Kb) types.13 SHIenable 0 Use the Serial Host Interface (USB), and disable all PC Card functions except attribute space, for access to theCOR and HCR for firmware debugging support. When = 0, use the Parallel Host Interface (PC Card or ISA).12 4Wire 1 Use 4-wire interface to SRAM (CS-, OE-, WEH-, WEL-) the ISL3873 x8 SRAMs. When = 0 selects 5-wireinterface for use with x16 SRAM (CS-, OE-, WE-, UBE-, LBE-).11 StrIdle 0 Start idle (wait for download from PC Card host interface).10 Mem16 0 RAM and NV space at startup is x 16. When = 0 RAM and NV space at startup is x 8. If starting from off-chip NVmemory this setting must indicate the width of the startup Flash Memory. During initialization, firmware can setseparate widths or RAM and NV space in the Memory Control Register.9 NVds 0 Disable mapping of off-chip control store to NV space (hence map off-chip control store to RAM space). When= 0 off-chip control store is mapped to NV memory8 ROMds 1 Disable on-chip control store ROM. When = 0 enable on-chip control store ROM.7 ISAmode 0 Set host interface control signals and address decoding for PC card. When = 1 set host interface signals andaddress decoding is for ISA bus, with all registers in I/O space and attribute space disabled. To use ISA mode,PHIenable must be = 1 to enable a parallel host interface.6 FCRinIO 0 Enable I/O space decoding for the physical FCRs. When = 1, the COR, CSR, and PRR registers are accessibleat I/O space offsets 0x40, 0x42, and 0x44 respectively. When = 0 these registers are only accessible in attributespace. This bit is ignored when PHIenable = 0, and is overridden (forced = 1) when ISAmode =1. FCRinIO = 1is useful for PC Card operation (PHIenable = 1, ISAmode = 0) to allow non-OS software to access the COR/HCRin OS environments where the system software does not permit application software to access attribute space.b5:0 Spare 0 x 00 Not assigned.a. FCRinIO = 1 forces HAMASK [0] = 1 to expand I/O space decoding from 0 x 40 to 0 x 80 bytes.TABLE 4. SERIAL EEPROM SELECTIONMD15 MD14 DEVICE TYPE FUNCTION0 0 AT45DB011 Large Serial Device used to transfer firmware to SRAM0 1 24C08 (Note) Small Serial Device which contains only CIS. MAC goes idle after loading CIS and waits for host.1 X None Modes not supported in firmware at this time. Consult factory for additional device types added.NOTE: The operating frequency of the serial port is 400kHz with a voltage of 3.3V.ISL3873
18Baseband ProcessorThe Baseband Processor operation is controlled by theISL3873 firmware. Detailed information on programming theBaseband Processor can be obtain by contacting the factory.BBP Packet ReceptionThe receive demodulator scrutinizes I and Q for packetactivity. When a packet arrives at a valid signal level thedemodulator acquires and tracks the incoming signal. It thensifts through the demodulator data for the Start FrameDelimiter (SFD). After SFD is detected, The BBP picks offthe needed header fields from the real-time demodulatedbitstream.Assuming all is well with the header, the BBP decodes thesignal field in the header and switches to the appropriatedata rate. If the signal field is not recognized, or the CRC16is in error, the demodulator will return to acquisition modelooking for another packet. If all is well with the header, andafter the demodulator has switched to the appropriate datarate, then the demodulator will continue to provide data tothe MAC in the ISL3873 indefinitely.RX I/Q A/D InterfaceThe PRISM baseband processor chip (ISL3873) includestwo 6-bit Analog to Digital converters (A/Ds) that sample thebalanced differential analog input from the IF down converterdevice (HFA3783). The I/Q A/D clock, samples at twice thechip rate with a nominal sampling rate of 22MHz.The interface specifications for the I and Q A/Ds are listed inTable 5. The ISL3873 is designed to be DC coupled to theHFA3783.The voltages applied to pin 16, VREF and pin 21, IREF setthe references for the internal I and Q A/D converters. Inaddition, For a nominal I/Q input of 400mVP-P, thesuggested VREF voltage is 1.2V.AGC CircuitThe AGC circuit as shown in Figure 12 is designed to adjustfor signal level variations and optimize A/D performance forthe I and Q inputs by maintaining the proper headroom onthe 6-bit converters. There are two gain stages beingcontrolled. At RF, the gain control is a 30dB step change.This RF gain control optimizes the receiver dynamic rangewhen the signal level is high and maintains the noise figureof the receiver when it is needed most at low signal level. AtIF, the gain control is linear and covers the bulk of the gaincontrol range of the receiver.The AGC loop is partially digital which allows for holding thegain fixed during a packet. The AGC sensing mechanism usesa combination of the I and Q A/D converters and the detectedsignal level in the IF to determine the gain settings. The A/Doutputs are monitored in the ISL3873 for the desired nominallevel. When it is reached, by adjusting the receiver gain, thegain control is locked for the remainder of the packet.RX_AGC_IN InterfaceThe signal level in the IF stage is monitored to determinewhen to impose the 30dB gain reduction in the RF stage.This maximizes the dynamic range of the receiver bykeeping the RF stages out of saturation at high signal levels.When the IF circuits’ sensor output reaches 0.5VDD, theISL3873 comparator switches in the 30dB pad and alsoadds 30dB of gain to the IF AGC amplifier. Thiscompensates the IF AGC and RSSI measures.TX I/Q DAC InterfaceThe transmit section outputs balanced differential analogsignals from the transmit DACs to the HFA3783. These areDC coupled and digitally filtered.Transmitter DescriptionThe ISL3873 transmitter is designed as a Direct SequenceSpread Spectrum Phase Shift Keying (DSSS PSK)modulator which is capable of handling data rates of up to11Mbps (refer to AC and DC specifications). The variousmodes of the modulator are Differential Binary Phase ShiftKeying (DBPSK) for 1Mbps, Differential Quaternary PhaseShift Keying (DQPSK) for 2Mbps, and Complementary CodeKeying (CCK) for 5.5Mbps and 11Mbps.CCK is essentially a quadra-phase form of M-ARY OrthogonalKeying. A description of that modulation can be found inChapter 5 of: “Telecommunications System Engineering”, byLindsey and Simon, Prentiss Hall publishing.The implemented data rates using a clock rate of 44MHz areshown in Table 6 and the modulation schemes are indicatedin Figure 13. The major functional blocks of the transmitterinclude a Processor Interface, Modulator, Data Scrambler,Preamble/Header Generator, TX Filter, AGC Control, andADC and DAC circuits. Figure 17 provides a basic blockdiagram of the DSSS Baseband Processor with anemphasis on the transmitter section. Figure 19 provides abasic block diagram of the DSSS Baseband Processor withan emphasis on the receive section.The preamble is always transmitted as the DBPSK waveformwhile the header can be configured to be either DBPSK, orDQPSK, and data packets can be configured for DBPSK,DQPSK, or CCK. The preamble is used by the receiver toTABLE 5. I, Q, A/D SPECIFICATIONSPARAMETER MIN TYP MAXFull Scale Input Voltage (VP-P) 0.90 1.00 1.10Input Bandwidth (-0.5dB) - 11MHz -Input Capacitance (pF) - 2 -Input Impedance (DC) 5kΩ--fS (Sampling Frequency) - 22MHz -ISL3873
19achieve initial Pseudo Noise (PN) synchronization while theheader includes the necessary data fields of thecommunications protocol to establish the physical layer link.The transmitter generates the synchronization preamble andheader and knows when to make the DBPSK to DQPSK orCCK switchover, as required.For the 1 and 2Mbps modes, the transmitter accepts datafrom the external source, scrambles it, differentially encodesit as either DBPSK or DQPSK, and spreads it with the BPSKPN sequence. The baseband digital signals are then outputto the external IF modulator.For the CCK modes, the transmitter inputs the data andpartitions it into nibbles (4 bits) or bytes (8 bits). At 5.5Mbps,it uses two of those bits to select one of 4 complex spreadsequences from a table of CCK sequences and then QPSKmodulates that symbol with the remaining 2 bits. Thus, thereare 4 possible spread sequences to send at four possiblecarrier phases, but only one is sent. This sequence is thenmodulated on the I and Q outputs. The initial phasereference for the data portion of the packet is the phase ofthe last bit of the header. At 11Mbps, one byte is used asabove where 6 bits are used to select one of 64 spreadsequences for a symbol and the other 2 are used to QPSKmodulate that symbol. Thus, the total possible number ofcombinations of sequence and carrier phases is 256. Ofthese only one is sent.Bit rates for the ISL3873 are defined in Table 6. This tableprovides information on bit rates, data rates and symbolrates for an MCLK of 44MHz clock. Figure 13 shows themodulation schemes for the different bits rates. Themodulator is completely independent from the demodulator,allowing the PRISM baseband processor to be used in fullduplex operation.Header/Packet DescriptionThe ISL3873 is designed to handle packetized DirectSequence Spread Spectrum (DSSS) data transmissions. TheISL3873 generates its own preamble and header information.It uses two packet preamble and header configurations. Thefirst is backwards compatible with the existing IEEE 802.11-1997 1 and 2Mbps modes and the second is the optionalshortened mode which maximizes throughput at the expenseof compatibility with legacy equipment.In the long preamble mode, the device uses asynchronization preamble of 128 symbols along with aheader that includes four fields. The preamble is all 1’s(before entering the scrambler) plus a Start Frame Delimiter(SFD). The actual transmitted pattern of the preamble israndomized by the scrambler. The preamble is alwaystransmitted as a DBPSK waveform (1Mbps). The duration ofthe long preamble and header is 192µs.In the short preamble mode, the modem uses asynchronization field of 56 zero symbols along with an SFDtransmitted at 1Mbps. The short header is transmitted at2Mbps. The synchronization preamble is all 0’s to distinguishit from the long header mode and the short preamble SFD isthe time reverse of the long preamble SFD. The duration ofthe short preamble and header is 96µs.Start Frame Delimiter (SFD) Field (16 Bits)This field is used to establish the link frame timing. TheISL3873 will not declare a valid data packet, even if it PNacquires, unless it detects the SFD. The ISL3873 receiverauto-detects if the packet is long or short preamble and setsSFD time-out. The timer starts counting after initialization ofthe de-scrambler is complete.RX_RF_AGCRX_IF_DET THRESH.IFDACI ADCQ ADCRX_Q±RX_I±RX_IF_AGCHFA3683 HFA3783ISL387366711I/ODEMODAGCDATA I/ODETECT CTLFIGURE 12. AGC CIRCUITTABLE 6. BIT RATE TABLE EXAMPLES FOR MCLK = 44MHzDATAMODULATION A/D SAMPLE CLOCK(MHz) TX SETUP CR 5BITS 1, 0 RX SIGNAL CR 63BITS 7, 6 DATA RATE(Mbps) SYMBOL RATE(MSPS)DBPSK 22 00 00 1 1DQPSK 22 01 01 2 1CCK 22 10 10 5.5 1.375CCK 22 11 11 11 1.375ISL3873
20Header FieldThe header field is defined by four fields which are shown inFigure 14. These fields are Signal Field, Service Field,Length Field and CITT-CRC16 Field. They are furtherdefined by the following:Signal Field (8 Bits) - This field indicates what data rate thedata packet that follows the header will be. The ISL3873receiver looks at the signal field to determine whether itneeds to switch from DBPSK demodulation into DQPSK, orCCK demodulation at the end of the preamble and headerfields.Service Field (8 Bits) - The MSB of this field is used toindicate the correct length when the length field value isambiguous at 11Mbps. See IEEE STD 802.11 for definitionof the other bits. Bit 2 is used by the ISL3873 to indicate thatthe carrier reference and the bit timing references arederived from the same oscillator (locked oscillators).Length Field (16 Bits) - This field indicates the number ofmicroseconds it will take to transmit the payload data(PSDU). The external controller (MAC) will check the lengthfield in determining when it needs to de-assert RX_PE.CCITT - CRC 16 Field (16 Bits) - This field includes the16-bit CCITT - CRC 16 calculation of the three header fields.This value is compared with the CCITT - CRC 16 codecalculated at the receiver. The ISL3873 receiver will indicatea CCITT- CRC 16 error via CR24 bit 2 and will lowerMD_RDY and reset the receiver to the acquisition mode ifthere is an error.The CRC or cyclic Redundancy Check is a CCITT CRC-16FCS (Frame Check Sequence). It is the ones complement ofthe remainder generated by the modulo 2 division of theprotected bits by the polynomial:x16 + x12 + x5 + 1The protected bits are processed in transmit order. All CRCcalculations are made ahead of data scrambling. A shiftregister with two taps is used for the calculation. It is presetto all ones and then the protected fields are shifted throughthe register. The output is then complemented and theresidual shifted out MSB first.The following Configuration Registers (CR) are used toprogram the preamble/header functions, more programmingdetails about these registers can be found in the ControlRegisters section of this document:802.11 DSSS BPSK 802.11 DSSS QPSK1MbpsBARKER 2MbpsBARKERDATAIOUTQOUTCHIPRATE1 BIT ENCODED TO 2 BITS ENCODED4 CODE WORDSSYMBOLRATEI vs. Q11 MC/S 11 MC/S1 MS/S 1 MS/S11 CHIPS 11 CHIPSTO ONE OFFIGURE 13. MODULATION MODESONE OF 2 CODEWORDS(TRUE-INVERSE)5.5Mbps CCK4 BITS ENCODED11 MC/S1.375 MS/S8 CHIPSCOMPLEXSPREAD FUNCTIONS TO ONE OF 16COMPLEX CCKCODE WORDS11Mbps CCK8 BITS ENCODED11 MC/S1.375 MS/S8 CHIPSCOMPLEXSPREAD FUNCTIONS TO ONE OF 256COMPLEX CCKCODE WORDSPREAMBLE (SYNC)128/56 BITS Start FRAME DELIMITER16 BITS SIGNAL FIELD8 BITS SERVICE FIELD8 BITS LENGTH FIELD16 BITS CRC1616 BITSHEADERPREAMBLEFIGURE 14. 802.11 PREAMBLE/HEADERISL3873
21CR 3 - Defines the short preamble length minus the SFD insymbols. The 802.11 protocol requires a setting of 56d = 38hfor the optional short preamble.CR 4 - Defines the long preamble length minus the SFD insymbols. The 802.11 protocol requires a setting of128d = 80h for the mandatory long preamble.CR 5 Bits 0, 1 - These bits of the register set the Signal fieldto indicate what modulation is to be used for the data portionof the packet.CR 6 - The value to be used in the Service field.CR 7 and 8 - Defines the value of the transmit data lengthfield. This value includes all symbols following the lastheader field symbol and is in microseconds required totransmit the data at the chosen data rate.The packet consists of the preamble, header and MAC ProtocolData Unit (MPDU). The data is transmitted exactly as receivedfrom the control processor. Some dummy bits will be appendedto the end of the packet to ensure an orderly shutdown of thetransmitter. This prevents spectrum splatter. At the end of apacket, the external controller is expected to de-assert theTX_PE line to shut the transmitter down.Scrambler and Data Encoder DescriptionThe modulator has a data scrambler that implements thescrambling algorithm specified in the IEEE 802.11 standard.This scrambler is used for the preamble, header, and data inall modes. The data scrambler is a self synchronizing circuit.It consists of a 7-bit shift register with feedback fromspecified taps of the register. Both transmitter and receiveruse the same scrambling algorithm. The scrambler can bedisabled by setting CR32 bit 2 to 1.NOTE: Be advised that the IEEE 802.11 compliant scrambler in theISL3873 has the property that it can lock up (stop scrambling) onrandom data followed by repetitive bit patterns. The probability of thishappening is 1/128. The patterns that have been identified are allzeros, all ones, repeated 10s, repeated 1100s, and repeated111000s. Any break in the repetitive pattern will restart the scrambler.To ensure that this does not cause any problem, the CCK waveformuses a ping pong differential coding scheme that breaks up repetitive0’s patterns.Scrambling is done by division with a prescribed polynomialas shown in Figure 15. A shift register holds the last quotientand the output is the exclusive or of the data and the sum oftaps in the shift register. The transmit scrambler seed for thelong preamble or for the short preamble can be set withCR48 or CR49.For the 1Mbps DBPSK data rates and for the header in all ratesusing the long preamble, the data coder implements thedesired DBPSK coding by differential encoding the serial datafrom the scrambler and driving both the I and Q outputchannels together. For the 2Mbps DQPSK data rate and for theheader in the short preamble mode, the data coder implementsthe desired coding as shown in the DQPSK Data EncoderTable 7. This coding scheme results from differential coding ofdibits (2 bits). Vector rotation is counterclockwise although bits6 and 7 of configuration register CR 1 can be used to reversethe rotation sense of the TX or RX signal if desired.Spread Spectrum Modulator DescriptionThe modulator is designed to generate DBPSK, DQPSK, andCCK spread spectrum signals. The modulator is capable ofautomatically switching its rate where the preamble isDBPSK modulated, and the data and/or header aremodulated differently. The modulator can support date ratesof 1, 2, 5.5 and 11Mbps. Quadraphase (I/Q) modulation isused at the baseband for all modulation modes. Furtherinformation on the programming details required to set upthe modulator can be obtained by contacting the factory.In the 1Mbps DBPSK mode, the I and Q Channels areconnected together and driven with the output of the scramblerand differential encoder. The I and Q Channels are then bothmultiplied with the 11-bit Barker word at the spread rate. The Iand Q signals go to the Quadrature upconverter (HFA3724) tobe modulated onto a carrier. Thus, the spreading and datamodulation are BPSK modulated onto the carrier.For the 2Mbps DQPSK mode, the serial data is formed intodibits or bit pairs in the differential encoder as detailedabove. One of the bits from the differential encoder goes tothe I Channel and the other to the Q Channel. The I and QChannels are then both multiplied with the 11-bit Barkerword at the spread rate. This forms QPSK modulation at thesymbol rate with BPSK modulation at the spread rate.CCK ModulationFor the CCK modes, the spreading code length is 8 complexchips and based on complementary codes. The chipping rate is11Mchip/s. The following formula is used to derive the CCKcode words that are used for spreading both 5.5 and 11Mbps:FIGURE 15. SCRAMBLING PROCESSZ-1 Z-2 Z-3 Z-4 Z-5 Z-6 Z-7XORSERIAL DATAIN XORSERIALDATA OUTTABLE 7. DQPSK DATA ENCODERPHASE SHIFT DIBIT PATTERN (d0, d1)d0 IS FIRST IN TIME000+90 01+180 11-90 10cejϕ1ϕ2ϕ3ϕ4+++()ejϕ1ϕ3ϕ4++()ejϕ1ϕ2ϕ4++(),ejϕ1ϕ4+()ejϕ1ϕ2ϕ3++()ejϕ1ϕ3+()ejϕ1ϕ2+()ejϕ1,–,,,–,,=ISL3873
22(LSB to MSB), where c is the code word.The terms: ϕ1, ϕ2, ϕ3, and ϕ4 are defined below for5.5Mbps and 11Mbps.This formula creates 8 complex chips (LSB to MSB) that aretransmitted LSB first. The coding is a form of the generalizedHadamard transform encoding where the phase ϕ1 is addedto all code chips, ϕ2 is added to all odd code chips, ϕ3 isadded to all odd pairs of code chips and ϕ4 is added to allodd quads of code chips.The phase ϕ1 modifies the phase of all code chips of thesequence and is DQPSK encoded for 5.5 and 11Mbps. Thiswill take the form of rotating the whole symbol by theappropriate amount relative to the phase of the precedingsymbol. Note that the last chip of the symbol defined aboveis the chip that indicates the symbol’s reference phase.For the 5.5Mbps CCK mode, the output of the scrambler ispartitioned into nibbles. The first two bits are encoded asdifferential symbol phase modulation in accordance with Table8. All odd numbered symbols of the MPDU are given an extra180 degree (π) rotation in addition to the standard DQPSKmodulation as shown in the table. The symbols of the MPDUshall be numbered starting with “0” for the first symbol for thepurposes of determining odd and even symbols. That is, theMPDU starts on an even numbered symbol. The last data dibitsd2, and d3 CCK encode the basic symbol as specified in Table9. This table is derived from the CCK formula above by settingϕ2 = (d2*pi)+ pi/2, ϕ3 = 0, and ϕ4 = d3*pi. In Table 9 d2 and d3are in the order shown and the complex chips are shown LSBto MSB (left to right) with LSB transmitted first.At 11Mbps, 8 bits (d0 to d7; d0 first in time) are transmittedper symbol.The first dibit (d0, d1) encodes the phase ϕ1 based onDQPSK. The DQPSK encoder is specified in Table 8 above.The phase change for ϕ1 is relative to the phase ϕ1 of thepreceding symbol. In the case of rate change, the phasechange for ϕ1 is relative to the phase ϕ1 of the precedingCCK symbol. All odd numbered symbols of the MPDU aregiven an extra 180 degree (π) rotation in accordance with theDQPSK modulation as shown in Table 8. Symbol numberingstarts with “0” for the first symbol of the MPDU.The data dibits: (d2, d3), (d4, d5), (d6, d7) encode ϕ2, ϕ3,and ϕ4 respectively based on QPSK as specified in Table10. Note that this table is binary, not Grey, coded.Transmit Filter DescriptionTo minimize the requirements on the analog transmit filtering,the transmit section shown in Figure 17 has an output digitalfilter. This filter is a Finite Impulse Response (FIR) style filterwhose passband shape is set by tap coefficients. This filtershapes the spectrum to meet the radio spectral maskrequirements while minimizing the peak to average amplitudeon the output. To meet the particular spread spectrumprocessing gain regulatory requirements in Japan on channel14, an extra FIR filter shape has been included that has awider main lobe. This increases the 90% power bandwidthfrom about 11MHz to 14MHz. It has the unavoidable sideeffect of increasing the amplitude modulation, so the availabletransmit power is compromised by 2dB when using this filter(CR 11 bit 5).TX Power ControlThe transmitter power can be controlled via two registers.The first register, CR58, contains the results of powermeasurements digitized by the ISL3873. By comparing thismeasurement to what is needed for transmit power, adetermination is made whether to raise or lower the transmitpower. It does this by writing the power level desired toregister CR31.Clear Channel Assessment (CCA) andEnergy Detect (ED) DescriptionThe Clear Channel Assessment (CCA) circuit implements thecarrier sense portion of a Carrier Sense Multiple Access(CSMA) networking scheme. The Clear Channel Assessment(CCA) monitors the environment to determine when it is clearto transmit. The CCA circuit in the ISL3873 can beprogrammed to be a function of RSSI (energy detected on thechannel), CS1, SQ1, or various combinations. The CCA isused by the Media Access Controller (MAC) in the ISL3873.The MAC decides on transmission based on traffic to sendand the CCA indication. The CCA indication can be ignored,allowing transmissions independent of any channelconditions. The CCA in combination with the visibility of theTABLE 8. DQPSK ENCODING TABLEDIBIT PATTERN (d(0), d(1))d(0) IS FIRST IN TIMEEVEN SYMBOLSPHASECHANGE(+jω)ODD SYMBOLSPHASECHANGE(+jω)00 0 π01 π/2 3π/2 (-π/2)11 π010 3π/2 (-π/2) π/2TABLE 9. 5.5Mbps CCK ENCODING TABLEd2, d3 CHIPS00 1j1 1j-1 1j1-1j101 -1j-1 -1j11j1-1j110 -1j1 -1j-1 -1j11j111 1j-1 1j1-1j11j1TABLE 10. QPSK ENCODING TABLEDIBIT PATTERN (d(i), d(i+1))d(i) IS FIRST IN TIME PHASE00 001 π/210 π11 3π/2 (-π/2)ISL3873
23various internal parameters (i.e., Energy Detectionmeasurement results), can assist the MAC in executingalgorithms that can adapt to the environment. Thesealgorithms can increase network throughput by minimizingcollisions and reducing transmissions liable to errors.There are three measures that can be used in the CCAassessment. The Receive Signal Strength Indication (RSSI)which indicates the energy at the antenna, CS1 and carriersense (SQ1). CS1 becomes active anytime the AGC portionof the circuit becomes unlocked, which is likely at the onset ofa signal that is strong enough to support 11Mbps, but may notoccur with the onset of a signal that is only strong enough tosupport 1 or 2MBps. CS1 stays active until the AGC locks anda SQ1 assessment is done, if SQ1 is false, then CS1 iscleared, which deasserts CCA. If SQ1 is true, then tracking isbegun, and CCA continues to show the channel busy. CS1may occur at any time during acquisition as the AGC statemachine runs asynchronously with respect to slot times.SQ1 becomes active only when a spread signal with theproper PN code has been detected, and the peak correlationamplitude to sidelobe ratio exceeds a set threshold, so itmay not be adequate in itself.A SQ1 evaluation occurs whenever the AGC has remainedlocked for the entire data ingest period. When this happens,SQ1 is updated between 8 and 9µs into the 10µs dwell. IfCS1 is not active, two consecutive SQ1’s are required toadvance the part to tracking.The state of CCA is not guaranteed from the time RX_PEgoes high until the first CCA assessment is made. At the endof a packet, after RXPE has been deasserted, the state ofCCA is also not guaranteed.The Receive Signal Strength Indication (RSSI) measurement isderived from the state of the AGC circuit. ED is the comparisonresult of RSSI against a threshold. The threshold may be set toan absolute power value, or it may be set to be N dB above themeasured noise floor. See CR 35. The ISL3873 measures andstores the RSSI level when it detects no presence of BPSK orQPSK signals. The average value of a 256 value buffer is takento be the noise floor. Thus, the value of the noise floor will adaptto the environment. A separate noise floor value is maintainedfor each antenna. An initial value of the noise floor isestablished within 50µs of the chip being active and is refinedas time goes on. Deasserting RX_PE does not corrupt thelearned values. If the absolute power metric is chosen, thisthreshold is normally set to between -70 and -80dBm.If desired, ED may be used in the acquisition process as wellas CCA. ED may be used to mask (squelch) weak signalsand prevent radio reception of signals too weak to supportthe high data rates, signals from adjacent cells, networks, orbuildings.The Configuration registers effecting the CCA algorithmoperation are summarized below (more programming detailson these registers can be found under the Control Registerssection of this document).The CCA output from pin 60 of the device can be defined asactive high or active low through CR 1 (bit 2).CR9(6:5) allows CCA to be programmed to be a function of EDonly, the logical operation of (CS1 OR SQ1), the logical functionof (ED AND (CS1 OR SQ1)), or (ED OR (CS1 OR SQ1)).CR9(7) lets the user select from sampled CCA mode, whichmeans CCA will not glitch, is updated once per symbol and isvalid for reading at 15.8µs or 18.7µs. In non-sampled mode,CCA may change at any time, potentially several times per slot,as ED and CS1 operate asynchronously to slot times.In a typical system CCA will be monitored to determine whenthe channel is clear. Once the channel is detected busy,CCA should be checked periodically to determine if thechannel becomes clear. Once MD_RDY goes active, CCAshould be ignored for the remainder of the message. Failureto monitor CCA until MD_RDY goes active (or use of a time-out circuit) could result in a stalled system as it is possible forthe channel to be busy and then become clear without anMD_RDY occurring.AGC DescriptionThe AGC system consists of the 3 chips handling the receivesignal, the RF to IF downconverter HFA3683, the IF tobaseband converter HFA3783, and the baseband processor(BBP) section of the ISL3873. The AGC loop (Figure 11) isdigitally controlled by the BBP. Basically it operates as follows:Initially, the receiver is set for high gain. The percent of timethat the A/D converters in the baseband processor aresaturated is monitored along with signal amplitude and thegain is adjusted down until the amplitude is what willoptimize the demodulator’s performance. If the amount ofsaturation is great, the initial gain adjust steps are large. Ifthe signal overload is small, they are less. When the gain isabout right and the A/Ds’ outputs are within the lock window(CR19), the BBP declares AGC lock and stops adjusting forthe duration of the packet. If the signal level then varies morethan a preset amount (CR20, CR29), the AGC is declaredunlocked and the gain again allowed to readjust.The BBP looks for the locked state following an unlockedstate (CS1) as one indication that a received signal is on theantenna. This starts the receive process of looking for PNcorrelation (SQ1). Once PN correlation and AGC lock arefound, the processor begins acquisition.For large signals, the power level in the RF stage output isalso monitored and if it is large, the LNA stage is shut down.This removes 30dB of gain from the receive chain which iscompensated for by replacing 30dB of gain in the IF AGCstage. There is some hysteresis in this operation and oncethe AGC locks, it is locked as well. This improves thereceiver dynamic range.ISL3873
24RX_RF_AGC Pad Operation30dB Pad Engaging (RF Chip Low Gain):If the AGC is not locked onto a packet, a '1' on theifCompDet input will engage in the 30dB attenuation pad.This causes the AGC to go out of lock and also forces theattenuation accumulator to be set to the programmed valueof CR27. The AGC then attempts to lock on the signal.If the AGC is locked on a packet, ifCompDet is ignored.30DB PAD RELEASING (RF CHIP HIGH GAIN):If the AGC is not locked onto a packet and the attenuationaccumulator sum falls below the programmable threshold(CR27), the pad will release. This is for the case where anoise spike kicked in the 30dB pad and the pad shouldrelease when the noise spike ends. Since the noise floor isdifferent for different environments, it is possible that in manycases CR27’s programmed value will be below the noise floorand the pad will not be removed except by RXPE going low.There is a recommended value to program CR27 (24dB), butthat depends on what environment the radio is in.During a packet (after AGC lock), the 30dB pad is heldconstant and the CR27 threshold is ignored.RXPE low forces the pad to release whether in the middle ofa packet or not. At the end of a packet, RXPE always goeslow, forcing the pad to release.Notes: The attenuation accumulator is basically about equal tothe current RSSI value.The accumulator output, after going through the interpolatorlookup table, feeds the AGC D/A.The pad value is programmable (CR17), but isrecommended to be set to 30dB.ifCompDet is a signal from the HFA3783 chip. A '1' indicatesits inputs are near saturation and it needs the RF chip toswitch from high gain to low gain.RX_IF_Det is the input to the ISL3873 chip which isconnected to ifCompDet on the HFA3783.RX_RF_AGC is the output of the ISL3873 chip and '1' is highgain, '0' is low gain.Demodulator DescriptionThe receiver portion of the baseband processor, performs A/Dconversion and demodulation of the spread spectrum signal.It correlates the PN spread symbols, then demodulates theDBPSK, DQPSK, or CCK symbols. The demodulator includesa frequency tracking loop that tracks and removes the carrierfrequency offset. In addition, it tracks the symbol timing, anddifferentially decodes and descrambles the data. The data isoutput through the RX Port to the external processor.The PRISM baseband processor in the ISL3873 usesdifferentially coherent demodulation. The ISL3873 isdesigned to achieve rapid settling of the carrier tracking loopduring acquisition. Rapid phase fluctuations are handledwith a relatively wide loop bandwidth which is then steppeddown as the packet progresses. Coherent processingimproves the BER performance margin as opposed todifferentially coherent processing for the CCK data rates.The baseband processor uses time invariant correlation tostrip the Barker code spreading and phase processing todemodulate the resulting signals in the header andDBPSK/DQPSK demodulation modes. These operations areillustrated in Figure 18 which is an overall block diagram ofthe receiver processor.In processing the DBPSK header, input samples from the I andQ A/D converters are correlated to remove the spreadingsequence. The peak position of the correlation pulse is used todetermine the symbol timing. The sample stream is decimatedto the symbol rate and corrected for frequency offset prior toPSK demodulation. Phase errors from the demodulator are fedto the NCO through a lead/lag filter to maintain phase lock. Thecarrier is de-rotated by the carrier tracking loop. Thedemodulated data is differentially decoded and descrambledbefore being sent to the header detection section.In the 1Mbps DBPSK mode, data demodulation is performedthe same as in header processing. In the 2Mbps DQPSKmode, the demodulator demodulates two bits per symboland differentially decodes these bit pairs. The bits are thenserialized and descrambled prior to being sent to the output.In the CCK modes, the receiver removes carrier frequencyoffsets and uses a bank of correlators to detect themodulation. A biggest picker finds the largest correlation inthe I and Q Channels and determines the sign of thosecorrelations. For this to happen, the demodulator must knowthe starting phase which is determined by referencing thedata to the last bit of the header. Each symbol demodulateddetermines 1 or 2 nibbles of data. This is then serialized anddescrambled before being passed to the output.Carrier tracking is via a lead/lag filter using a digital Costasphase detector. Chip tracking in the CCK modes is chipdecision directed or slaved to the carrier tracking dependingon whether or not the locked oscillator design is utilized inthe radio.Acquisition DescriptionA projected worst case time line for the acquisition of asignal with a short preamble and header is shown. Thesynchronization part of the preamble is 56 symbols longfollowed by a 16-bit SFD. The receiver must monitor theantenna to determine if a signal is present. The timeline isbroken into 10µs blocks (dwells) for the scanning process.This length of time is necessary to allow enough integrationof the signal to make a good acquisition decision. This worstcase time line example assumes that the signal arrives partway into the first dwell such as to just barely catch detection.The signal and the scanning process are asynchronous andthe signal could start anywhere. In this timeline, it isassumed that the signal is present in the first 10µs dwell, butwas missed due to power amplifier ramp up.ISL3873
25Meanwhile signal quality and signal frequencymeasurements are made simultaneous with symbol timingmeasurements. A CS1 followed by SQ1 active, or twoconsecutive SQ1s will cause the part to finish the acquisitionphase and enter the tracking phase.Prior to initial acquisition the NCO is inactive (0Hz) andcarrier phase measurement are done on a symbol by symbolbasis. After acquisition, coherent DPSK demodulation is ineffect. After a brief setup time as illustrated on the timeline,the signal begins to emerge from the demodulator.It takes 7 more symbols to seed the descrambler before validdata is available. This occurs in time for the SFD to be received.At this time the demodulator is tracking and in the coherentPSK demodulation mode so it will no longer acquire newsignals. If a much larger signal overrides the signal beingdemodulated (a collision), the demodulator will abort thetracking process and attempt to acquire the new signal. Failureto find an SFD within the SFD timeout interval will result in areceiver reset and return to acquisition mode.2 20 SYMBOLS56 SYMBOL SYNC SFDTXPOWERRAMP20 SYMBOLS 7 SYM 16 SYMBOLSAGC SETTLE AND LOCK VERIFY AND CIR/FREQUENCYSFD DETSEEDFIGURE 16. ACQUISITION TIMELINE, NON DIVERSITYAND INITIAL DETECTION ESTIMATION AND CMF/NCOJAMMINGDESCRAMBLERSTART SFD SEARCHSTART DATAPREAMBLE/HEADERCRC-16TX_AGC_INVREFIREFANTSELCCATX_DATASCRAMBLER TXDPROCESSORRXCLKMODULATOR,TXI+/-TXQ+/-BARKER/CCKTIMINGGENERATORVDDA (ANALOG) VDD (DIGITAL)GND (ANALOG) GND (DIGITAL) TXCLK TX_RDYTX_PEANTSELTRANSMITPORTMCLKMCLKFIGURE 17. DSSS BASEBAND PROCESSOR, TRANSMIT SECTIONTX AGCCONTROLTRANSMITFILTEROUTPUT MUXTEST CONTROLOUTPUT MUXDACDACTXSTATECONTROLTX_IF_AGCGENERATOR6-BITDACREGISTER6-BITADCMACCONTROLSIGNALSINTERNALINTERFACESIGNALSISL3873
26Channel Matched Filter (CMF) DescriptionThe receive section shown in Figure 19 operates on theRAKE receiver principle which maximizes the SNR of thesignal by combining the energy of multipath signalcomponents. The RAKE receiver is implemented with aChannel Matched Filter (CMF) using a FIR filter structure with16 taps. The CMF is programmed by calculating the ChannelImpulse Response (CIR) of the channel and mathematicallymanipulating that to form the tap coefficients of the CMF.Thus, the CMF is set to compensate the channelcharacteristics that distort the signal. Since the calculation ofthe CIR is inaccurate at low SNR or in the presence of strongCW interference, the chip has thresholds (CR 36 to 39) thatare set to substitute a default CMF shape under thoseconditions. This default CMF shape is designed tocompensate only the known transmit and receive non linearity.PN Correlators DescriptionThere are two types of correlators in the ISL3873 basebandprocessor. The first is a parallel matched filter correlator thatcorrelates for the Barker sequence used in preamble,header, and PSK data modes. This Barker code correlator isdesigned to handle BPSK spreading with carrier offsets upto ±50ppm and 11 chips per symbol. Since the spreading isBPSK, the correlator is implemented with two realcorrelators, one for the I and one for the Q Channel. Thesame Barker sequence is always used for both I and Qcorrelators.These correlators are time invariant matched filtersotherwise known as parallel correlators. They use onesample per chip for correlation although two samples perchip are processed. The correlator despreads the samplesfrom the chip rate back to the original symbol rate giving10.4dB processing gain for 11 chips per symbol. Whiledespreading the desired signal, the correlator spreads theenergy of any non correlating interfering signal.The second form of correlator is the parallel correlator bankused for detection of the CCK modulation. For the CCKmodes, the 64 wide bank of parallel correlators isimplemented with a Fast Walsh Transform to correlate the 4or 64 code possibilities. This greatly simplifies the circuitryof the correlation function. It is followed by a biggest pickerwhich finds the biggest of 4 or 64 correlator outputsdepending on the rate. This is translated into 2 or 6 databits. The detected output is then processed through thedifferential phase decoder to demodulate the last two bitsof the symbol.Data Demodulation and TrackingDescription (DBPSK and DQPSK Modes)The signal is demodulated from the correlation peakstracked by the symbol timing loop (bit sync) as shown inFigure 18. The frequency and phase of the signal iscorrected using the NCO that is driven by the phase lockedloop. Averaging the phase errors over 10 symbols gives thenecessary frequency information for seeding the NCOoperation.Data Decoder and DescramblerDescriptionThe data decoder that implements the desired DQPSKcoding/decoding as shown in Table 11. The data is formedinto pairs of bits called dibits. The left bit of the pair is the firstin time. This coding scheme results from differential codingof the dibits. Vector rotation is counterclockwise for a positivephase shift, but can be reversed with bit 7 or 6 of CR 1.For DBPSK, the decoding is simple differential decoding.The data scrambler and de-scrambler are self synchronizingcircuits. They consist of a 7-bit shift register with feedback ofsome of the taps of the register. The scrambler is designedto ensure smearing of the discrete spectrum lines producedby the PN code.One thing to keep in mind is that both the differentialdecoding and the descrambling cause error extension orburst errors. This is due to two properties of the processing.First, the differential decoding process causes errors tooccur on pairs of symbols. When a symbol’s phase is inerror, the next symbol will also be decoded wrong since thedata is encoded in the change in phase from one symbol tothe next. Thus, two errors are made on two successivesymbols. Therefore up to 4 bits may be wrong although onthe average only 2 are. In QPSK mode, these may occurnext to one another or separated by up to 2 bits. In the CCKmode, when a symbol decision error is made, up to 6 bitsmay be in error although on average only 3 bits will be inerror. Secondly, when the bits are processed by thedescrambler, these errors are further extended. Thedescrambler is a 7-bit shift register with two taps exclusiveor’ed with the bit stream. Thus, each error is extended by afactor of three. Multiple errors can be spaced the same asthe tap spacing, so they can be canceled in the descrambler.In this case, two wrongs do make a right. Given all that, if asingle error is made the whole packet is discarded anyway,so the error extension property has no effect on the packeterror rate. It should be taken into account if a forward errorcorrection scheme is contemplated.Descrambling is self synchronizing and is done by apolynomial division using a prescribed polynomial. A shiftregister holds the last quotient and the output is the exclusive-or of the data and the sum of taps in the shift register.TABLE 11. DQPSK DATA DECODERPHASE SHIFT DIBIT PATTERN (D0, D1)D0 IS FIRST IN TIME000+90 01+180 11-90 10ISL3873
27Data Demodulation in the CCK ModesIn this mode, the demodulator uses Complementary CodeKeying (CCK) modulation for the two highest data rates. It isslaved to the low rate processor which it depends on foracquisition of initial timing and phase tracking information.The low rate section acquires the signal, locks up symboland carrier tracking loops, and determines the data rate tobe used for the MPDU data.The demodulator for the CCK modes takes over when thepreamble and header have been acquired and processed.On the last bit of the header, the phase of the signal iscaptured and used as a phase reference for the high ratedifferential demodulator.The signal from the A/D converters is carrier frequency andphase corrected by a DESPIN stage. This removes thefrequency offset and aligns the I and Q Channels properly forthe correlators. The sample rate is decimated to 11MSPS forthe correlators after the DESPIN since the data is nowsynchronous in time.The demodulator knows the symbol timing, so thecorrelation is batch processed over each symbol. Thecorrelation outputs from the correlator are compared to eachother in a biggest picker and the chosen one determines 6bits of the symbol. The QPSK phase of the chosen onedetermines two more bits for a total of 8 bits per symbol. Sixbits come from which of the 64 correlators had the largestoutput and the last two are determined from the QPSKdifferential demod of that output. In the 5.5Mbps mode, only4 of the correlator outputs are monitored. This demodulates2 bits for which of 4 correlators had the largest output and 2more for the QPSK demodulation of that output for a total of4 bits per symbol.Equalizer DescriptionThe ISL3873 employs a Decision Feedback Equalizer (DFE)to improve performance in the presence of significantmultipath distortion. The DFE combats Inter ChipInterference (ICI) and Inter Symbol Interference (ISI). Theequalizer is trained on the sample data collected during thefirst part of the acquisition after the AGC has settled and theantenna selected. The same data is used for CMFcalculations and equalizer training. Once the equalizer hasbeen set up, it is used to process the incoming symbols in adecision feedback manner. After the Fast Walsh transform isperformed, the detected symbols are corrected for ICI beforethe bigger picker where the symbol decision process isperformed. Once a symbol has been demodulated, thecalculated residual energy from that symbol is subtractedfrom the incoming data for the next symbol. That corrects forthe ISI component. The DFE is not adapted during thepacket as the channel impulse response is not expected tovary significantly during that brief time. Register CR10 bits 4and 5 can disable these equalizers separately.TrackingCarrier tracking is performed on the de-rotated signalsamples from the complex multiplier in a four phase Costasloop. This forms the error term that is integrated in the lead/lagfilter for the NCO, closing the loop. Tracking is only measuredwhen there is a chip transition. Note that this tracking isdependent on a positive SNR in the chip rate bandwidth.The symbol clock is tracked by a sample interpolator thatcan adjust the sample timing forwards and backwards by 72increments of 1/8th chip. This approach means that theISL3873 can only track an offset in timing for a finite intervalbefore the limits of the interpolator are reached. Thus,continuous demodulation is not possible.Locked Oscillator TrackingSymbol tracking can be slaved to the carrier offset trackingfor improved performance as long as at both the transmittingand the receiving radios, the bit clocks and carrier frequencyclocks are locked to common crystal oscillators. A bit carriedin the SERVICE field (bit 2) indicates whether or not thetransmitter has locked clocks. When the same bit is set atthe receiver (CR6 bit 2), the receiver knows it can track thebit clock by counting down the carrier tracking offset. This ismuch more accurate than tracking the bit clock directly.CR33 bit 6 can enable or disable this capability.T0 + 1 SYMBOL CORRELATORCORRELATIONT0 + 2 SYMBOLST0SAMPLESEARLYON-TIMELATECORRELATION TIMEFIGURE 18. CORRELATION PROCESSPEAKAT 2X CHIPRATECORRELATOR OUTPUT IS THE RESULT OF CORRELATINGTHE PSEUDO NOISE(PN) SEQUENCE WITH THE RECEIVED SIGNAL OUTPUT REPEATSISL3873
28PREAMBLE/HEADERCRC-16 DETECT6-BITA/D 66CORRELATORCLEAR CHANNELASSESSMENT/BITSYNCRX_DATADESCRAMBLERMUXRXD TO MACTIMINGGENERATOR88RX_IF_AGCTEST CONTROLPEAKEXTRACT.SIGNAL QUALITYMCLK6-BITA/DBARKERDOWN CONVERTANTENNASWITCHCONTROLNCOLOOPFILTEREQUAL.BIASADDERSYMBOLDECISIONFIGURE 19. DSSS BASEBAND PROCESSOR, RECEIVE SECTIONVDDA (ANALOG) VDD (DIGITAL)GND (ANALOG) GND (DIGITAL)TXITXQMCLKINTERPOLATINGCCKDPSKDEMODAGC6-BITDACRX_RF_AGCRX_IF_DETCONTROL6-BITDAC6-BITDACMUXRECEIVESTATEMACHINERXCLK TO MACSYMBOLTRACKINGMD_RDY TO MACRXIRXQRESETANTSELCMFTRAININGRX_PECORRELANTSELCHANNELMATCHED FILTERBUFFERCOHERENTINTEGRATORTIMINGDIVERSITYCONTROLANT SELDECISION FEEDBACKEQUALIZERCCA toMAC(INTERNAL)INTERNAL TRANSMITAND RECEIVESIGNALS TO MACISL3873
29Demodulator PerformanceThis section indicates the typical performance measures fora radio design. The performance data below should be usedas a guide. In general, the actual performance depends onthe application, interference environment, RF/IFimplementation and radio component selection.Overall Eb/N0 Versus BER PerformanceThe PRISM chip set has been designed to be robust andenergy efficient in packet mode communications. Thedemodulator uses coherent processing for datademodulation. The figures below show the performance ofthe baseband processor when used in conjunction with theHFA3783 IF and the PRISM recommended IF filters. Off theshelf test equipment are used for the RF processing. Thecurves should be used as a guide to assess performance ina complete implementation.Factors for carrier phase noise, multipath, and otherdegradations will need to be considered on animplementation by implementation basis in order to predictthe overall performance of each individual system.Figure 18 shows the curves for theoretical DBPSK/DQPSKdemodulation with coherent demodulation anddescrambling as well as the PRISM performance measuredfor DBPSK and DQPSK. The theoretical performance forDBPSK and DQPSK are the same as shown on thediagram. Figure 21 shows the theoretical and actualperformance of the CCK modes. The losses in both figuresinclude RF and IF radio losses; they do not reflect theISL3873 losses alone. The ISL3873 baseband processinglosses from theoretical are, by themselves, a smallpercentage of the overall loss.The PRISM demodulator performs with an implementationloss of less than 4dB from theoretical in a AWGNenvironment with low phase noise local oscillators. For the1 and 2Mbps modes, the observed errors occurred ingroups of 4 and 6 errors. This is because of the errorextension properties of differential decoding anddescrambling. For the 5.5 and 11Mbps modes, the errorsoccur in symbols of 4 or 8 bits each and are furtherextended by the descrambling. Therefore the error patternsare less well defined.Clock Offset Tracking PerformanceThe PRISM baseband processor is designed to accept dataclock offsets of up to ±25ppm for each end of the link (TXand RX). This effects both the acquisition and the trackingperformance of the demodulator. The budget for clock offseterror is 0.75dB at ±50ppm. No appreciable degradation wasseen for operation in AWGN at ±50ppm. Symbol tracking isaccomplished by one of two methods. If both ends of the linkemploy locked oscillators for their bit timing and carrierfrequency generation, symbol tracking is done by dividingdown the carrier frequency offset. If either one of the ends ofthe link do not have locked oscillators, then symbol trackingis done by a conventional early-late chip tracking method.Carrier Offset Frequency PerformanceThe correlators used for acquisition for all modes and fordemodulation in the 1 and 2Mbps modes are time invariantmatched filter correlators otherwise known as parallelcorrelators. They use two samples per chip and are tappedat every other shift register stage. Their performance withcarrier frequency offsets is determined by the phase roll ratedue to the offset. For an offset of +50ppm (combined for bothTX and RX) will cause the carrier to phase roll 22.5 degreesover the length of the correlator. This causes a loss of0.22dB in correlation magnitude which translates directly toEb/N0 performance loss. In the PRISM chip design, thecarrier phase locked loop is inactive during acquisition.During tracking, the carrier tracking loop corrects for offset,so that no degradation is noted. In the presence of highmultipath and high SNR, however, some degradation isexpected.FIGURE 20. BER vs Eb/N0 PERFORMANCE FOR PSK MODESFIGURE 21. BER vs Eb/N0 PERFORMANCE FOR CCK MODES789101112Eb/N01.E+00BER1.E-031.E-041.E-051.E-071.E-081.E-021.E-061.E-01BER 1.0THY 1, 2BER 2.0141312111098765BEREb/N01.E+001.E-031.E-041.E-051.E-071.E-081.E-021.E-061.E-011.E-09BER 11BER 5.5THY 5.5THY 11ISL3873
30RSSI PerformanceThe RSSI value is reported on CR62 in hex and is linear withsignal level in dB. Figure 22 shows the RSSI curvemeasured on a whole evaluation radio. This takes intoaccount the full gain adjust range of all radio parts. To getsignal level in dBm on a radio, simply subtract the RSSIvalue in decimal from 100.Signal Quality EstimateA signal quality measure is available on CR51 for use by theMAC. This measure is the SNR in the carrier tracking loopand can be used to determine when the demodulator isworking near to the noise floor and likely to make errors.Figure 23 shows the performance of the SQ measure versussignal to noise level.ED ThresholdThe performance of the ED threshold is shown in Figure 24.Setting this threshold will effect CCA only. Using ED as partof the CCA measure will allow deferral to large signals evenif they are not correlated to the desired spread signals.ED can be read from CR61 bit 4. Using ED and RSSI canassist the MAC in determining the presence of noncorrelating signals such as frequency hoppers or microwaveovens. For example, the MAC can elect to try to transmitover microwave oven interference but not count the results inrate shifting algorithms.-100 -80 -60 -40 -20 0120100806040200SIGNAL LEVEL IN dBmRSSI IN DERSSIFIGURE 22. RSSI vs SIGNAL LEVEL-10 -5 0 5 10 15 20 250102030405060708090100SNR IN THE SPREAD BANDWIDTH AT 1MbpsPERMEANSTDDEVFIGURE 23. SIGNAL QUALITY MEASURE AND PER vs SNR4020100-10 02010 30 4030ED THRESHOLD VALUE IN DECIMALSNR IN SPREAD BANDWIDTHSTARTS MISSINGMISSINGFIGURE 24. ED THRESHOLD vs SNR IN dB AT 1MbpsISL3873
31All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/quality/iso.asp.Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How-ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use.No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.For information regarding Intersil Corporation and its products, see web site www.intersil.comSales Office HeadquartersNORTH AMERICAIntersil Corporation2401 Palm Bay Rd., Mail Stop 53-204Palm Bay, FL 32905TEL: (321) 724-7000FAX: (321) 724-7240EUROPEIntersil SAMercure Center100, Rue de la Fusee1130 Brussels, BelgiumTEL: (32) 2.724.2111FAX: (32) 2.724.22.05ASIAIntersil Ltd.8F-2, 96, Sec. 1, Chien-kuo North,Taipei, Taiwan 104Republic of ChinaTEL: 886-2-2515-8508FAX: 886-2-2515-8369ISL3873Plastic Ball Grid Array Packages (BGA)oTOP VIEWDA1BOTTOM VIEWPNLMJKGHFE81314 12 11 10 9CORNER765 342CDAB1SIDE VIEWSEATING PLANECAA1A2 bbbCaaaA1EABE1D1bSALL ROWS AND COLUMNSSM A BCC0.150.08 M0.0060.003 A1A1CORNER I.D.eAACRT1516CORNERCORNER I.D.V192.14x14192 BALL PLASTIC BALL GRID ARRAY PACKAGESYMBOLINCHES MILLIMETERSNOTESMIN MAX MIN MAXA - 0.059 - 1.40 -A1 0.012 0.016 0.31 0.41 -A2 0.033 0.039 0.83 0.99 -b 0.016 0.020 0.41 0.51 7D/E 0.547 0.555 13.90 14.10 -D1/E1 0.468 0.476 11.90 12.10 -N 192 192 -e 0.032 BSC 0.80 BSC -MD/ME 16 x 16 16 x 16 3bbb 0.004 0.10 -aaa 0.005 0.12 -Rev. 1 1/01NOTES:1. Controlling dimension: MILLIMETER. Converted inchdimensions are not necessarily exact.2. Dimensioning and tolerancing conform to ASME Y14.5M-1994.3. “MD” and “ME” are the maximum ball matrix size for the “D”and “E” dimensions, respectively.4. “N” is the maximum number of balls for the specific array size.5. Primary datum C and seating plane are defined by the spher-ical crowns of the contact balls.6. Dimension “A” includes standoff height “A1”, package bodythickness and lid or cap height “A2”.7. Dimension “b” is measured at the maximum ball diameter,parallel to the primary datum C.8. Pin “A1” is marked on the top and bottom sides adjacent to A1.9. “S” is measured with respect to datum’s A and B and definesthe position of the solder balls nearest to package center-lines. When there is an even number of balls in the outer rowthe value is “S” = e/2.

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